• Corpus ID: 17892454

Design Guidance for the Mechanical Reliability of Low-K Flip Chip BGA Package

@inproceedings{Chang2004DesignGF,
  title={Design Guidance for the Mechanical Reliability of Low-K Flip Chip BGA Package},
  author={Kuo-Chin Chang and Yuan Li and Chung-yi Lin and M. J. Lii},
  year={2004},
  url={https://api.semanticscholar.org/CorpusID:17892454}
}
Flip Chip Ball Grid Array (FCBGA) package has been introduced in recent years to address the needs in the microelectronic packaging industry for increasing performance and I/O density, which offers a cost effective solution with smaller form factor. Furthermore, Cu interconnects with low-k dielectric material were also introduced to reduce power consumption and further enhance device performance. Due to the nature of low-k dielectric material characteristics, it is more sensitive while a… 
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9 References

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater…

Analysis of flip-chip packaging challenges on copper/low-k interconnects

An interfacial-fracture-mechanics-based simulation methodology has been developed to study the flip-chip packaging effect on the copper/low-k structures. Multilevel submodeling techniques have been…

Effect of packaging on interfacial cracking in Cu/ low k Damascene structures

In this study, 3D f~te element analysis (FEA) based on a multilevel sub-modeling approach in combination with highresolution moire interferometry was employed to examine the packaging effect on low k…

Interfacial adhesion study for copper/SiLK interconnects in flip-chip packages

    M. MillerP. Ho
    Materials Science, Engineering
    2001 Proceedings. 51st Electronic Components and…
  • 2001
This paper presents the results of a two-part study to determine the fracture toughness of relevant interfaces within Cu/SiLK low-k interconnect structures and relate those data to the actual driving…

Failure analysis of solder bumped flip chip on low-cost substrates

    J. LauC. ChangS. Lee
    Engineering, Materials Science
    Twenty Fourth IEEE/CPMT International Electronics…
  • 1999
Failure analyses of 63wt%Sn-37wt%Pb solder bumped flip chip assemblies with underfill encapsulant are presented in this study. Emphasis is placed on solder flowed-out, nonuniform underfill and voids,…

Thermal stress and debonding in Cu/low k damascene line structures

In this study, the thermal stress and debond characteristics of Cu damascene structures were investigated using X-ray diffraction and 3D finite element analysis (FEA). First, X-ray diffraction was…

Enhancement of flip-chip fatigue life by encapsulation

Encapsulation of controlled collapse chip connection (C4) joints, using a filled epoxy resin with a matched coefficient of thermal expansion (CTE), has provided a substantial increase in the life of…

Effects of dielectric material and linewidth on thermal stresses of Cu line structures

Thermal stresses of Cu line structures of 0.4 and 0.2 /spl mu/m linewidth integrated with fluorinated silicon oxide SiOF and two kinds of low k dielectrics, carbon doped oxide CDO and organic polymer…